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SX1211
WIRELESS & SENSING
3. Architecture Description
This section describes in depth the architecture of this ultra low-power transceiver:
VR_PA
RFIO
PA
I
LO1 Tx
I
Q
LO2 Tx
Waveform
generator
Q
I
Q
LO2 Tx
RSSI
LNA
LO2 Rx
OOK
demod
FSK
demod
BitSync
Control
IRQ_0
IRQ_1
MOSI
MISO
SCK
NSS_CONFIG
LO1 Rx
LO1 Rx
NSS_DATA
CLKOUT
DATA
TEST(8:0)
I LO2 Rx
XTAL_P
XTAL_M
XO
Frequency Synthesizer
LO
Generator
Q
PLL_LOCK
Q
I
LO1 Tx
I LO2 Tx
Q
Figure 3: SX1211 Detailed Block Diagram
3.1. Power Supply Strategy
To provide stable sensitivity and linearity characteristics over a wide supply range, the SX1211 is internally
regulated. This internal regulated power supply structure is described below:
Rev 8 – February 2013
Page 12 of 92
www.semtech.com
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